The invention relates to an integrated electronic multiplex circuit which includes N (N&gt;1) data inputs, a data output for a multiplexed signal, a clock input for receiving a clock signal, and a start input for receiving a start signal. Data on the N data inputs appears sequentially on the data output, after the occurence of a first state of the binary start signal, under the control of the clock signal.
The invention also relates to an integrated electronic circuit which includes a multiplex circuit.
A circuit of this kind is disclosed in Digest of Technical Papers of the IEEE International Solid State Circuits Conference, pages 206-207 which shows a block diagram of a video memory which includes a multiplex circuit. However, it is not shown how this circuit can be realized. The conversion of a constant stream of parallel data into an uninterrupted multiplexed signal at a very high clock frequency (for example, some tens of MHz) imposes special requirements on the multiplex circuit. Moreover, the multiplex circuit must be suitable for integration on the same semiconductor substrate as the memory field.
The multiplex circuit in said video memory could be constructed by using a switching network with transfer gates (as in the known Philips IC HEF 4512B) and a binary counter. The start signal sets a given count in the binary counter, which count is incremented by each clock signal pulse. The counter indicates the data input which is connected by the switching network to the data output for generating the multiplexed signal thereon. However this solution is too slow for use with such high clock frequencies; moreover it occupies a large amount of surface area when it is integrated. The switching network includes a number of parallel conductors which apply the control signals from the counter to the transfer gates. Particularly at such high clock frequencies the invariably occurring phase differences between the signals on these parallel conductors cause disturbances in the multiplexed signal, which are more pronounced as the clock frequency increases and which ultimately inhibit the supply of relevant data by the multiplex circuit.